Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferroelectric semiconductor memory devices. Other ferroelectric materials, for example, strontium bismuth tantalate (SBT) can also be used. The ferroelectric material is located between two electrodes to form a ferroelectric capacitor for storage of information. Ferroelectric capacitor uses the hysteresis polarization characteristic of the ferroelectric material for storing information. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. To change the polarization of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. The polarization of the capacitor depends on the polarity of the voltage applied. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
FIG. 1 shows a diagram of a portion of an IC. The portion includes first and second bitlines 107a-b with ferroelectric memory cells 105a-b. The bitlines, for example, form a bitline pair in a memory block or array. For purposes of simplifying the discussion, each bitline is depicted with one memory cell. However, it is understood that typically each bitlines includes a plurality of memory cells. A memory cell 105 includes a transistor 130 coupled to a capacitor 140. One terminal of the transistor is coupled to a bitline while the other terminal is coupled to a first electrode of the capacitor. The second capacitor electrode is coupled to a plateline 106. The first electrode is referred to as the top electrode (TE) and the second electrode is referred to as the bottom electrode (BE). A wordline 104 is coupled to the gate of the transistor The bitline pair is coupled to a sense amplifier (SA) 109.
The bitline coupled to the non-inverting terminal (+) of the SA is referred to as the bitline true (BL) and the bitline coupled to the inverting terminal (−) of the SA is referred to as the bitline complement (/BL).
To write to one of the memory cells of the bitline pair, the SA drives the bitlines to a voltage level which is on the data line DQ and the plate line is pulsed between a high and low voltage level. The appropriate wordline is selected, coupling the capacitor to its respective bitline. The voltage on the bitline and pulse create an electric field across the capacitor, causing the capacitor to have a polarization based on the electric field.
When using differential amplifiers, the assignment of physical direction of the polarization of the storage capacitor to the logical information stored in the memory cell depends on whether the selected cell is coupled to BL or /BL. For example, if a logic 0 is written to a memory cell on the bitline pair, the resulting voltage on BL would be a low voltage and a high voltage on /BL. As a result, the polarization direction of capacitor 140a on BL would be TE-BE while the polarization direction of capacitor 140b on /BL would be BE-TE.
To read from a memory cell, the SA precharges the bitlines to, for example, 0 volts. After the bitlines are precharged, the appropriate wordline is selected and a logic 1 pulse is provided on the plateline. The pulse, for example, is about 2.5 V. The pulse creates an electric field across the selected capacitor. This field produces a voltage or a read signal on the bitline to which the cell is coupled. The SA drives a reference voltage onto the bitline of the non-selected cell. The sense amplifier senses the differential of the read signal with the reference voltage and amplifies it. For example, a differential signal greater than or less than the reference voltage represents a logic 1 or 0. The larger the differential, the greater the signal-to-noise ratio or the larger the sensing window.
FIG. 2 shows the read signal distribution for the cells on BL and /BL. For example, the bolded lines 280 and 281 represent the read signal of logic 0 and logic 1for cells located on BL and the lighter lines 290 and 291 represent the read signal of logic 0 and logic 1 for cells located on /BL. As shown, the asymmetry that exists between the cells on BL and /BL has created a two fold distribution in the read signals. This undesirably reduces the differential between the read signal and reference voltage or sensing window 278, which can increase failures.
From the foregoing discussion, it is desirable to reduce the broadening of the read signal distribution to improve the sensing window.